The present invention relates to electronic circuits, and in particular, to phase-lock loops.
In modern technologies, signals having gigahertz frequency, requiring phase-lock loops are the foundation for various applications. A phase-lock loop (PLL) is a circuit that generates a periodic output signal having a constant phase relationship with respect to a periodic input signal.
FIG. 1 shows a block diagram of a conventional charge pump-based phase-lock loop 100. Phase/frequency detector (PFD) 102 compares the phase θRef of the input signal FRef to the phase θback of the feedback signal Fback and generates an error signal, either an up signal (when θRef leads θback) or a down signal (when θback leads θRef), where the width of the error signal pulse indicates the magnitude of the difference between θRef and θBack.
Charge pump 104 generates an amount of charge equivalent to the error signal (either up or down) from PFD 102. Depending on whether the error signal is an up signal or a down signal, the charge is either added to or subtracted from the capacitors in loop filter 106. In this description, the loop filter 106 has a relatively simple design, comprising a capacitor Cs in parallel with the series combination of a resistor R and a relatively large capacitor CL. As such, loop filter 106 operates as an integrator that accumulates the net charge from charge pump 104, and the architecture is also known as a charge pump-based loop filter. Other, more-sophisticated loop filters are of course also possible. The resulting loop-filter voltage VLF is applied to voltage-to-current converter (V2C) 108, and a corresponding current ILF is applied to the current control oscillator (CCO) 110. A CCO is a device that generates aperiodic output signal (Fosc in FIG. 1), whose frequency is a function of the CCO input current (CLF in FIG. 1). In addition to being the output signal from PLL 100, the CCO output signal Fosc is used to generate the feedback signal FBack for the closed-loop PLL circuit.
An optional feedback divider 112 is placed in the feedback path, respectively, if the frequency of the output signal Fosc is to be either a fraction or a multiple of the frequency of the input signal FRef. If not, the feedback divider applies a factor of 1 to the feedback signals, respectively.
Due to the effect of the feedback path in PLL 100, the steady-state output signal Fosc, will have a fixed phase relationship with respect to the input signal FRef. Unless some phase offset is purposely added, the phases of the input and output signals will be synchronized with minimal offset.
FIG. 4a shows a transfer curve according to the diagram in FIG. 1, where the input voltage VLF induces a corresponding output oscillating signal at frequency Fosc through the V2C and CCO. For low-noise PLL applications, it is important for CCO 108 in FIG. 1 to have a relatively low gain. This implies that the slope of the transfer curve should be relatively low, such as those shown in FIG. 4b. It is therefore desirable to design a selectable operating curve for the CCO to generate a stable oscillating loop signal.
Conventionally, each CCO is tested in the factory to characterize its set of operating curves to pre-determine which digital control input values (i.e. N=2 in FIG. 4b) are appropriate for different desired output frequencies. When a particular CCO is selected for a particular application, such as PLL 100 of FIG. 1, the appropriate operating curve is permanently burned into the device. This factory testing and hard-wiring of the CCO adds to the cost of manufacturing the PLLs. It also limits the operating frequency range of each PLL to the permanently selected operating curve.